1. Field of the Invention
The present invention relates to a semiconductor device in which data stored in a memory cell is read out to a bit line and amplified by a sense amplifier, and particularly relates to a semiconductor device employing a memory cell including a select transistor with a floating body structure.
2. Description of Related Art
In a semiconductor memory device such as DRAM (Dynamic Random Access Memory), 1T1C type memory cells each including a capacitor and a select transistor are often used. Generally, in this type of memory cells, a PN junction is formed between a storage electrode of the capacitor and a body of the select transistor. It is known that leak current at the storage electrode of the memory cell increases in proportion to electric field intensity at the PN junction between the body and the storage electrode of the capacitor. Thus, in order to reduce the leak current of the memory cell, it is required to reduce the electric field intensity applied to the PN junction. Here, the potential of the PN junction in a conventional memory cell will be explained as a first related technique with reference to FIG. 14. FIG. 14 shows a schematic cross sectional view of the memory cell using the select transistor with a bulk type MOS structure, in which an N-type impurity layer 301 (source region) connected to a bit line BL and an N-type impurity layer 302 (drain region) connected to a storage electrode 306 of a capacitor Cs are formed on an upper region of a P-type silicon substrate 300, and an element isolation insulating film 303 is formed around the impurity layers 301 and 302. Over the P-type silicon substrate 300 functioning as the body of the select transistor, there is formed a gate electrode 305 connected to the word line WL via a gate dielectric film 304. Here, in the capacitor Cs, a plate voltage VPLT is applied to a plate electrode 307, the storage electrode 306 maintains a voltage VSN, and a substrate voltage VBB is applied to the P-type silicon substrate 300. A potential state in the select transistor in this case is shown in a graph of FIG. 15, in which the potential is rapidly changes at a position of the PN junction formed along a path (having relative positions on a horizontal axis) from the drain to the P-type silicon substrate 30. A potential difference occurring at this point in the PN junction is VSN−VBB+Vbi (Vbi is a built-in potential in a thermal equilibrium state). In the example of FIG. 15, it is assumed that VSN=1V, VBB=−0.5 and Vbi=0.6V, and the potential difference in case where the memory cell stores HIGH data is about 2.1V. The electric field intensity applied to the PN junction increases in proportion to the potential difference occurring in the PN junction and densities of P- and N-type impurities in a portion of the PN junction.
A second related technique for reducing the electric field intensity at the above PN junction in the memory cell has been proposed. For example, Patent References 1 and 2 disclose a technique for reducing the electric field applied to the PN junction by reducing the plate voltage VPLT applied to the capacitor Cs of the memory cell and reducing the voltage VSN of the storage electrode 306 using capacitance coupling during a period when a refresh operation is not performed in a self refresh mode (data retention mode) of the DRAM. For example, in a case where the voltage VSN of the storage electrode 306 is 1V when HIGH data is stored in the memory cell and is 0V when LOW data is stored therein, the plate voltage VPLT is usually set to 0.5V as an intermediate voltage. Then, the reduction of the electric field applied to the PN junction can be achieved by reducing the plate voltage VPLT. The potential state of the select transistor in this case is shown in a graph of FIG. 16, in which both voltage values including VSN=0.5V for the HIGH data and VSN=−0.5V for the LOW data decrease in comparison with FIG. 15, and the potential occurring in the PN junction is reduced from 2.1V (the first related technique) to 1.6V so as to reduce the leak current. In this example, even if the leak current occurs when storing the LOW data, the voltage VSN decreases and destruction of the stored data in the memory cell can be prevented, and thus it is not particularly necessary to consider the electric field intensity.    [Patent Reference 1] Japanese Patent Application Laid-open No. H8-22693    [Patent Reference 2] International Publication. No. WO2006-060249 (corresponding to U.S. Pat. No. 7,082,073)    [Non-Patent Reference 1] T. Yamauchi et al., “High-Performance Embedded SOI DRAM Architecture for the Low-Power Supply,” IEEE J. Solid-State Circuits, vol. 35, pp. 1169-1178, August 2000.
However, when employing the above conventional technique, the plate voltage VPLT needs to be returned to 0.5V for all memory cells before starting operations of sensing or refreshing for the bit line BL. Therefore, a restore time is necessary and consumption current increases, and thus a problem arises in that the technique cannot be adapted to a normal operation mode (external access mode) in which sensing operations are frequently repeated.
Meanwhile, Non-Patent Reference 1 discloses a technique capable of reducing the voltage VSN of the storage electrode 306 in a data retention state by driving the plate voltage VPLT with a pulse signal in a write operation of the memory cell (capacitor) using a floating body type select transistor with an SOI structure. For example, the voltage VSN of the storage electrode 306 is 0.8V when the memory cell stores the HIGH data and is −0.6V when the memory cell stores the LOW data. However, the Non-Patent Reference 1 discloses that the potential of the bit line BL is set to 0.4V in a precharge operation. Therefore, when the memory cell stores the LOW data, strong electric field is applied to the PN junction between the body and the bit line BL, and thus a problem arises in that the leak current increases when the LOW data is stored in the memory cell.